Verilog for Design and Verification

About Course

VLSI summer internship is a 30 hours of theory and labs course focused on providing Btech 2nd and 3rd year students with exposure to Verilog design and verification. Course also provides expertise on GVIM text editor.

...Verilog language constructs with detailed examples on each construct usage
Multiple Design Coding & Testbench development
Hands on labs & Hands on projects


How Verilog differs from other programming languages?
Verilog language concepts
Registers, nets
Vectors, Array
Data types
Various styles of Modeling: Data Flow, Behavioral, Gate level, Switch level
Procedural Blocks
Continuous assignments
Procedural Statements
State Machines
Gate Level Implementation
Hierarchical modeling
FSM : Mealy and Moore
FSM State encoding styles
Flipflop (Synchronous & Asynch Reset), Latch
Counter-Gray code counter, modulo, ring, johnson, up counter, down counter
Shift register implementation
Half adder, full adder, multiplexer
encoder, decoder, various gates
Pattern detector
Traffic light controller(TLC)
Synchronous FIFO
Asynchronous FIFO
Memory implementation
example to showcase race condition using blocking assignments
system task usage: $display, $monitor, $strobe
Clock generation with Duty cycle & Jitter

Course videos


Benefits of eLearning:

  • - Access to the Instructor - Ask questions to the Instructor who taught the course
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  • - Learn at Your Pace - VLSIGuru eLearning courses are self-paced, so you can proceed when you're ready

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