DMA controller is an important aspect of every SOC, which is used for peripheral to peripheral, peripheral to memory and memory to memory data transfers with minimal intervention from Processor. Current DMA controller design has 2 cores with 8 channels per core.
DMA controller functional verification using SV & UVM, covers all the aspects of verification starting from reading the specifications, feature list down, testbench development, testbench component coding, register model development, testcase coding and regression setup, debug for coverage analysis. Course gives indepth overview of sequence development, debugging of complete testcases, etc. Course also introduces to functional and code coverage analysis.