FPGA Design and Verification Training

About Course

FPGA course is a 6 months course provides in depth exposure to complete FPGA system design flow starting from RTL coding, prototyping and validation.

FPGA Architecture
FPGA internals and I/0
FPGA timing closure
FPGA implementation by RTL mode as well as IP Mode
FPGA debugging
Software development kit environment
Booting FPGA in petalinux/ubuntu


RTL coding, lint checks
RTL integration
Connectivity checks
Functional Verification
Synthesis & STA
Gate level simulations
Power aware simulations
Placement and Routing
Custom layout
Post silicon validation
Digital Design basics
combinational logic
sequential logic, FF, latch, counters
Refer to Advanced digital design training page for detailed course contents
File and directory management
User administration
Environment variables
Commonly used commands
Shell scripting basics
SEd and AWK
Revision management
SOC Architecture overview
SOC design concepts
SOC verification concepts
SOC Components
SOC use cases
SOC Testbench architecture
SOC Test Case coding
SOC verification differences with module verification
Verilog language constructs
Verilog design coding examples covering more than 20 standard designs
PAL, CPLD and FPGA basics
FPGA Design Flow
Internals of FPGA and CPLD
Logic implementation
FPGA Architectures of various FPGA vendors
Anti-fuse and SRAMS
Logic elements and Look-up Tables
Dedicated multipliers
Distributed RAM
Shift registers
Virtex Architectures
Introduction and usage of IP cores·
Modelsim/Icarus Verilog simulation
Design Synthesis
Design constraining and pin locking
Timing analysis
slack calculation
Data loss due to large skew
Maximum skew calculations with examples
Period constraints
Area and Power Constraints
Static Timing Analysis
FPGA programming
Floor plan
Place and Route
Post map and Post P&R simulation
XDC constraints
Reading and analysing reports-post synthesis
Post map simulation
Post P·&R simulation
Configuring FPGAs
FSM Extraction
Timing Simulation using Modelsim/Icarusverilog
Programming using JTAG
Debugging techniques
Debugging using chip scope and Logic analyzers
Protocols on FPGA
High Speed SERDES
Identification of the issues/resolving
FPGA SDK environment
FPGA Device selection
PERL Interpreter
File management
Regular expressions
Object oriented PERL
PERL modules
Facing interviews effectively
industry work culture
Group discussions
100+ detailed assignments covering all aspects from VLSI Flow, SOC Design, Verilog, Advanced digital design, System verilog, AXI protocol, VIP Development, RTL debug, UNIX and PERL scripting

Course videos

Unit 1 FPGA DEMO SES1 00:59:13
Unit 2 FPGA SES2 02:32:08
Unit 3 FPGA SES3 02:30:10
Unit 4 FPGA SES4 02:31:38
Unit 5 FPGA SES5 00:51:18
Unit 6 FPGA SES6 02:14:41
Unit 7 FPGA SES7 01:05:14
Unit 8 FPGA SES8 01:06:02
Unit 9 FPGA SES9 02:05:28
Unit 10 FPGA SES10 01:23:12
Unit 11 FPGA SES11 01:36:07
Unit 12 FPGA SES12 02:12:13
Unit 13 FPGA SES13 01:33:15
Unit 14 FPGA SES14 01:06:49
Unit 15 FPGA SES15 01:07:14
Unit 16 FPGA SES16 00:59:51
Unit 17 FPGA SES17 02:32:02
Unit 18 FPGA SES18 02:18:43
Unit 19 FPGA SES19 00:51:27
Unit 20 FPGA SES20 00:44:51
Unit 21 FPGA SES21 01:07:58
Unit 22 FPGA SES22 00:21:24
Unit 23 FPGA SES23 01:59:16
Unit 24 FPGA SES24 02:56:00
Unit 25 FPGA SES25 01:03:57

Benefits of eLearning:

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